Exemplary embodiments of the present invention relate to a semiconductor integrated circuit design, and more particularly, to a semiconductor integrated circuit (IC) having a chip-on-chip structure.
A wire bonding technology has been used to integrate a control semiconductor IC and a main semiconductor IC into a single package. However, if semiconductor ICs are packaged using wire bonding, there is a limitation in increasing the operating speed of the semiconductor ICs.
To solve this limitation, a chip-on-chip package technology, which stacks a control semiconductor IC and a main semiconductor IC in a vertical direction, is widely used. The chip-on-chip package technology is a package technology which identifies positions of both bump pads between a control semiconductor IC and a main semiconductor IC, and directly connects both bump pads without the use of wires. Such a chip-on-chip package technology increases an operating frequency due to high-speed signal transmission, reduces total power consumption, and minimizes an entire chip area.
However, if the chip-on-chip package technology is applied, the bump pad size of the semiconductor IC is too small (e.g., 30-μm×30-μm) to perform a probe test on the bump pads in a test mode. Therefore, in order to achieve a normal probe test, a probe test pad having a size of about 60-μm×60-μm must be separately provided.
Meanwhile, in addition to the above-described package technology, a structure in which an input bump pad and an output bump pad are separated from each other is applied to the semiconductor IC having the chip-on-chip structure. Given this structure, a load is further reduced in comparison to the case where data is inputted/outputted using a single bump pad.
Consequently, there is a need for a semiconductor IC design, which is suitable for a probe test, and where input/output bump pads are separated from each other.